A random access solid state memory device, such as a DRAM, SRAM, VRAM, ROM, EPROM, EEPROM, and others, stores and accesses data at specific cells located in a large array or groups of smaller arrays on the memory device. Such a memory device is referred to herein as a device under test ("DUT"). A memory tester tests the memory cells of a DUT by writing data into the cells and then reading data from the cells to determine whether the data read corresponds to the data written.
Any desired cell, or group of cells, is typically accessed by providing an address to the DUT. Address decoders within the DUT decode the address to enable the desired cell(s) in the array. The address is usually divided into two parts, often called row and column, or X and Y addresses, which are separately decoded. Each of the two address parts specifies a subgroup of the entire array. The desired cell or cells are the intersection of the two subgroups.
In some DUTs, the state representing a logic 1 datum stored in one cell might be the state that represents logic 0 datum stored in some other cell. The specific architecture of the DUT determines which state within each cell represents a logic 0 datum and which state represents logic 1 datum. This architectural definition of logic states is called the data topology of the DUT. For example, a logic 1 may be represented by a high voltage in some cells, and by a low voltage in other cells.
The mapping of the address to the actual physical location of the memory cell(s) can, and usually does, vary among different DUTs. When testing the DUTs, it is often useful to test cells by storing specific data in physically adjoining cells. Regardless of the procedure for testing cells, the memory tester needs to be properly implemented or configured so that memory cells are accurately tested in relation to one another. If the same memory tester is intended for use with several different DUTs, it is important that the address mapping be easily and flexibly configured for each DUT.
A common way for the memory tester to scan through the DUT addresses is to employ two address counters that separately generate addresses for the two DUT address decoders. Referring to FIG. 1, a prior art memory tester 10 tests a one megabit DUT having ten row address bits and ten column address bits. Tester 10 includes a 10-bit row address counter 14 and a 10-bit column address counter 16. The outputs of row counter 14 and column counter 16 are encoded by a row encoder 22 and a column encoder 24, respectively. Row encoder 22 and column encoder 24 operate in complementary manner to the DUT decoding process performed by a DUT row decoder 26 and a DUT column decoder 28 so that the memory cells are scanned in a physical order. Row encoder 22 and column encoder 24 are not reprogrammable. Memory testing with two non-reprogrammable logic encoders works very well with only one specific type of device and, thus, is not very flexible.
It is also common for memory testers to be implemented with a programmable address converter (sometimes called a translator) that is positioned between the row and column address counters and the DUT address input pins. The address converter, which may comprise a fast memory array, translates the counter outputs to activate the proper DUT address inputs. The fast memory array could be either a read-write memory loaded with the proper translation data or a preprogrammed read-only-memory.
For example, in the case of a one-megabit DUT, a converter with twenty input bits and twenty output bits could provide every possible combination of address mapping between the twenty output bits of the row and column address counters and the twenty input bits of the DUT. However, this would require a twenty megabit memory array in the converter to test a one megabit DUT. Additional memory would be required to take into account data topology. Accordingly, using a single memory array to translate the tester addresses into the DUT addresses is not generally practical because it requires too large a converter memory. The large memory is expensive, would increase the size of the tester, and would probably degrade tester performance.
A more practical alternative is to provide two separate address converters. For example, referring to FIG. 2, a prior art memory tester 30 includes respective row and column address converters (or translators) 36 and 38, each having a 1024.times.10 bit memory array. The 10-bit row count from row counter 14 is applied to row address converter 36, the 10 output bits of which address the row inputs of the DUT. The 10-bit column count from column counter 16 is applied to column address converter 38, the 10 output bits of which address the column inputs of the DUT. The two 1024.times.10 bit arrays 36 and 38 constitute 20 kilobits. There is, therefore, a thousandfold decrease in required memory bits (20 kilobits compared to 20 megabits) by using two 10-bit arrays 36 and 38, rather than one 20-bit array. For most devices, data topology can be added by merely making each array one bit larger (i.e., 1024.times.11 bits), and using the extra two bits to determine the data polarity.
A drawback to the use of two separate converters is that they do not provide sufficient flexibility for certain DUTs. For example, certain DUTs require that some of the row addresses be known to translate the column addresses and/or some of the column addresses be known to translate the row address. Sometimes the cells are interleaved, such as the teeth of two combs can be interleaved, so that adjacent cells might alternate between two different rows or columns. In addition, oftentimes the data topology is a Boolean function of several row and column addresses. The Boolean function could be as simple as an exclusive-or of one row and one column address, or it could be a combination of row addresses that select a combination of column addresses to determine data polarity. Both cases require that row and column addresses be used in combination to translate either the row or column addresses.
There is, therefore, a need for a memory tester that is implemented with an address converter that requires minimal memory space, but is sufficiently flexible to be compatible with DUTs of various types.